acq2106_set_sync_role
Usage
usage: acq2106_set_sync_role.py [-h] [--master_clk MASTER_CLK] [--master_trg MASTER_TRG] [--clkdiv CLKDIV] [--test TEST] [--trace TRACE]
[--slave_sync_trg_to_clk SLAVE_SYNC_TRG_TO_CLK]
uuts [uuts ...]
Positional Arguments
- uuts
uuts m1 [s1 s2 …]
Named Arguments
- --master_clk
master_clk role alt fp,sampleclk[,sysclk]
Default: “zclk,2000000”
- --master_trg
master_trg src alt: fp
Default: “soft,rising”
- --clkdiv
clock divider, each module
Default: “1”
- --test
test link
Default: 0
- --trace
set command tracing
Default: 0
- --slave_sync_trg_to_clk
0: do NOT retime the trg on the slave
Default: “0”
Outline:
acq2106_set_sync_role uuts
DEPRECATION WARNING: please consider using user_apps/acq400/sync_role.py
acq2106_set_sync_role
positional arguments: uuts uuts m1 [s1 s2 …]
optional arguments: -h, –help show this help message and exit –master_clk MASTER_CLK master_clk role alt fp,sysclk,sampleclk –master_trg MASTER_TRG master_trg src alt: fp –clkdiv CLKDIV clock divider, each module –test TEST test link –trace TRACE set command tracing