sync_role

Usage

usage: sync_role.py [-h] [--clk CLK] [--trg TRG] [--sim SIM] [--trace TRACE] [--auto_soft_trigger AUTO_SOFT_TRIGGER] [--clear_counters]
                    [--enable_trigger ENABLE_TRIGGER] [--toprole TOPROLE] [--fclk FCLK] [--fin FIN] [--clkdiv CLKDIV] [--downstream_bypass DOWNSTREAM_BYPASS]
                    [--si5326_bypass SI5326_BYPASS] [--trgsense TRGSENSE]
                    uuts [uuts ...]

Positional Arguments

uuts: uut

Named Arguments

--clk

int|ext|zclk|xclk,fpclk,SR,[FIN]

--trg

int|ext,rising|falling

--sim

s1[,s2,s3..] list of sites to run in simulate mode

--trace

1 : enable command tracing

--auto_soft_trigger

force soft trigger generation

Default: 0

--clear_counters

clear all counters SLOW

Default: False

--enable_trigger

0:leave disabled, 1 enable and drop out, 99 to enable at end

Default: 0

--toprole

role of top in stack

Default: “master”

--fclk

sample clock rate

Default: “1000000”

--fin

external clock rate

Default: “1000000”

--clkdiv

optional clockdiv

--downstream_bypass

provide full rate clock downstream

Default: 0

--si5326_bypass

bypass Si5326

Default: 0

--trgsense

trigger sense rising unless falling specified

Default: “rising”

Outline:

set sync roles for a stack of modules

expand_role(args, urole)[source]

configure_slave(name, args, postfix)[source]

set_sync_role(args)[source]

get_parser()[source]